This invention relates to data processing systems which include computing devices, and more particularly to an improved arithmetic system for performing floating-point computations.
In computing devices employing floating-point arithmetic capability, the data or operands upon which arithmetic functions are to be performed are in a format such that one portion of the data word contains the actual information and is called the mantissa. A second portion of the data words contains the signals indicative of the relative position of the arithmetic point, such as decimal or binary point, of the information contained in the mantissa, and is referred to as the characteristic. To perform arithmetic operations on data on the floating-point format, the actual arithmetic operations are performed on the signals of the mantissa portion of the data words, and the characteristics are used primarily to indicate the relative positions of the floating-point operands under consideration, and are utilized in determining the characteristic of the result of the arithmetic operation. For example, in adding two floating-point operands, each having its own characteristic and mantissa, arithmetic section of the data processing system utilizes the two characteristics to determine the actual digit-by-digit alignment of the mantissa portions in preparation for performing the floating-point arithmetic operation. For an add operation, the aligned mantissas are added together to form a new floating-point mantissa, and a resultant floating-point word is generated as a result of the combination of the newly formed mantissa with the characteristics. Floating-point substraction, multiplication, division, or format conversion, all involve manipulation of the characteristic.
The floating-point data words are stored, transferred, and processed, via a plurality of multiple-bit registers. Each bit position of a register represents a power of the radix of the register, and the modulus of the register is the radix raised to the power indicated by the number of bit positions of the register. For example, a 1's complement six-bit register has a modulus 2.sup.6, with the least significant bit position having a value 2.sup.0, with each increasing bit position having a value of 2 raised to the power designated by the bit position. For use with operands in floating-point format, the registers must utilize sufficient bit positions for holding the representation of the mantissa the characteristic. For single-precision format, the entire operand comprised of the sign, characteristic, and mantissa, is contained in a single register, however, the portion devoted to the mantissa is independent of the portion devoted to the characteristic. These entities are handled substantially independently.
The bit capacity of registers in the data processing system often relate to the number of bit positions in the memory registers. Operands in the floating-point format that are contained within the number of bit positions of a memory register capacity are often referred to as single-precision floating-point operands. The limitation of the number of bit positions to a single register obviously places limitations on the capacity and precision of the arithmetic manipulations. In order to increase the capacity of the floating-point operands, systems have been developed that utilize two full operands to comprise a single floating-point operand. This effectively doubles the bit capacity, and is commonly referred to as double-precision floating-point operation. In the double-precision format, the characteristic often times utilizes more bit positions than would be utilized for the single-precision format. In computing systems that utilize both single-precision and double-precision formats, systems have been devised for converting floating-point operands between the two systems of representation. For those systems that utilize a different number of bit positions to represent the characteristics between single-precision and double precision, it is necessary that the conversion between formats provide for adjustment of the characteristic representation. Further, it is necessary that there be adjustments of the mantissa when the conversion is from double-precision to single-precision format, it is common to require that the number of the characteristic bits be reduced, and that certain bit positions in the mantissa be dropped. During the converse conversion, the number of bit positions of the characteristic is increased, and the additional number of bit positions of the mantissa is made available.
Both the characteristic and mantissa for floating-point arithmetic operations, whether they be single- or double-precision, may represent positive or negative values. The sign bit referenced represents the sign of the mantissa. To avoid using two separate sign designations, that is, one for the characteristic and one for the mantissa, within the same operand, a system of characteristic biasing has been developed to indicate the sign of the characteristic. For example, a single-precision floating-point operand that provides for an eight-bit characteristic, can express numerical values ranging from 0 through octal 377. By arbitrarily applying a bias of octal 200 to the actual characteristic, the zero point is effectively shifted and permits the numerical representation of minus octal 200 through octal 177. In this manner, the value of the characteristic indicates whether it is positive or negative, with those characteristic values having a numerical value of octal 200 or less, representing negative characteristic values. A similar biasing system is applied to double-precision characteristics, with the same purpose. For example, if an eleven-bit characteristic is utilized, a bias of octal 2000 establishes a mid-point with numerical values of octal 2000 or less being of a negative value and characteristic values of more than octal 2000 being of a positive value. It can be seen, of course, that when converting between a single- and double-precision formats, the biasing as well as the bit capacity must be adjusted.
In performing conversion from double-precision floating-point to single-precision floating-point, care must be taken to establish that the magnitude of the double-precision characteristic can be expressed in a number of bit positions available in the single-precision format. In the event that a double-precision floating-point characteristic has a numerical value greater than the upper positive range of the single-precision floating-point characteristic, an overflow fault will occur, and an indication of this failure should be provided. Similarly, a double-precision floating-point characteristic on the lower extremity of the range that extends beyond the bit capacity of the single-precision floating-point operand cannot be accurately converted, and will cause an underflow fault to occur. The characteristic biasing system, the conversion from double-precision floating-point to single-precision floating-point and for conversion from single-precision floating-point to double-precision floating-point is described in detail in U.S. Pat. No. 3,389,379 to G. J. Erickson, et al.
When adding or subtracting two floating-point operands, it is necessary that each of the mantissa portions be aligned so that bit-positions having similar weights will be properly added. The alignment is determined by the examination of each of the characteristic portions. Normally, it would be desirable to subtract the smaller characteristic from the larger characteristic to determine the amount of shift for proper alignment of the smaller floating-point operand. In practice, however, it is generally not known which of the two available floating-point operands is the larger. For two characteristic values X and Y, the shift count for alignment purposes has been generated by the use of two adders producing the differences X-Y and Y-X, and thereafter selecting the positive result. This requires the use of two adders and requires some additional selection time. Since the alignment process must be accomplished before the actual computation can progress, any time that can be saved will enhance the overall operation of the data processing system. Of course, any hardware that can be saved will decrease the cost of the system. Other approaches have been developed, utilizing relatively complex circuitry mixing computations between 1's complement computation with 2's complement computation.
Prior art floating-point data processing systems have not provided adder assistance for use in characteristic calculations that provide for the generation of the functions X-Y or Y-X dependent upon the relative values of X and Y such that the absolute value of the difference between X and Y is provided along with a signal specifying which of the two characteristics is the smaller numerical value. Further, prior art systems have not provided for detection of overflow and underflow faults in the characteristic adder. Prior art systems have not provided characteristic adders that can handle two characteristic formats for use in single-precision and double-precision calculations while providing the absolute value of the difference between X and Y and the signal defining which of the two characteristics is the smaller of the two.